1. Field of the Invention
The present invention relates to a method for manufacturing high voltage transistors, and more particularly, to a three-dimensional high voltage transistor manufacturing method capable of increasing the length and width of the channels while reducing transistor forming area in a plane, and completely separating devices from each other while restraining parasitic capacitance, latch-up phenomena, and formation of field transistors.
2. Description of the Related Art
Generally, since high voltage transistors must withstand high voltages, their size is increased, because all items, such as the depths of the junction, the lengths of channel, and the thickness of oxide films of gates, must be able to withstand high voltage.
Thus, in order to manufacture the high voltage transistors, the volume of channel width×(length+length of an active for forming a contact)×depth of a well is required.
Although the area required for forming the high voltage transistor varies depending upon the required breakdown voltage (BV) and electric current, when a BV of about 10V is required, as shown in FIG. 1, the area occupies a large area of channel width×(length+length of an active for forming a contact)×depth of well region=20 μm×(1.5˜2 μm+1.1×2)×(1˜2 μm)=74˜84 μm3.
At that time, the active length for forming the contact is 0.4 μm (contact)+0.35×2(side overlap) and 1.1 μm.
Since problems occur, such as latch-up, parasitic capacitance, and turning-on of the field transistor when the required BV is increased, the channels and the junctions are reinforced by a method using extended drain and deep junction. However, according to the method for reinforcing the channels and the junctions, when the required BV is increased, the occupied area is increased in proportion to the increased BV.